1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to an SRAM (Static Random Access Memory) cell and a method for fabricating the same.
2. Discussion of the Related Art
In general, the SRAM cell consists either four transistors (for example, 2 access transistors and 2 drive transistors) and 2 polysilicon load resistors or 6 transistors. In particular, a highly integrated cell of 4 M class and over has 6 transistors in the form of CMOS including, in general, 4 NMOS transistors and 2 PMOS transistors. In an SRAM cell of lower integration, an asymmetrical cell is used, which is favorable in view of the occupied area. As the cell becomes highly integrated with a reduction of the occupied area, in which the asymmetry significantly affects the performance of the cell, a symmetrical cell becomes essential. However, with symmetry, a bit area becomes larger for the same line width Accordingly, a current major interest is to reduce the area while maintaining the symmetry.
FIG. 1 illustrates an equivalent circuit of a conventional CMOS SRAM cell. As shown, the conventional SRAM cell includes 4 NMOS transistors Q.sub.1.about.Q.sub.4 formed on a semiconductor substrate and 2 PMOS transistors Q5 and Q6 formed on the NMOS transistors as thin film transistors.
A conventional method for fabricating the SRAM cell having the aforementioned system will be explained with reference to the attached drawings. FIG. 2a illustrates a plan view showing an arrangement of bulk transistors in the conventional SRAM cell. FIG. 2b illustrates a plan view showing an arrangement of thin film transistors in the conventional SRAM cell. FIG. 3 illustrates a plan view showing an arrangement of the thin film transistors in FIG. 2b over the bulk transistors in FIG. 2a in the conventional SRAM cell. FIG. 4 illustrates a section of the conventional SRAM cell across a line IV--IV in FIG. 3. FIG. 5 illustrates a section of the conventional SRAM cell across a line V--V in FIG. 3.
Referring to the drawings, in the conventional method for fabricating an SRAM, a semiconductor substrate 31 is provided, and active regions 32 and field regions 32a are defined on the semiconductor substrate 31. A first gate oxide film 33 is formed on each of the active regions 32. A first polysilicon and a cap gate nitride film 34 are formed in succession on the first gate oxide film 33 and photoetched to define a first gate electrode 35 of a bulk transistor. Sidewall oxide films 37 are formed on both sides of the first gate electrodes 35. The first gate electrode 35 and the sidewall oxide films 37 on both sides thereof are used as masks in injecting impurity ions to form first and second impurity regions 39 and 41 in the active regions 32. A first interlayer insulating film 43 is formed on the entire surface over the semiconductor substrate 31 and etched to open a predetermined portion of the semiconductor substrate 31. A second polysilicon is deposited on the first interlayer insulating film 43 to be in contact with the first impurity region 39 to form a Vss line 44. Then, a second interlayer insulating film 45 and a third polysilicon are formed in succession on the Vss line 44. The third polysilicon is patterned with a photo-etching process to form a second gate electrode 46 of the thin film transistor. A second gate oxide film 47 and fourth polysilicon are formed on the semiconductor substrate 31, and an offset mask 48 is covered thereon. P type impurities are doped on the offset mask 48 to form a body 49 of a thin film transistor having source, drain and channel regions. In order to improve a transistor performance, heat treatment is carried out to increase the grain sizes. The SRAM cell is completed when processed through exposure, etching, and wiring. That is, an insulating film 50 is formed on the entire surface inclusive of the body 49 of the thin film transistor, and a contact hole to expose a surface of the first impurity region 39 is formed. Then, a metal wiring 51 is formed on the entire surface inclusive of the contact hole.
However, the aforementioned conventional SRAM cell and method for fabricating the same have the following problems. First, the asymmetry of the drive transistors and access transistors places a limitation on the reduction of a cell size. Second, the difference in the channel directions of the drive transistors and access transistors complicates the fabrication process of the memory cell. Third, the spaced formation with certain intervals and a connection of the gates to one another in a later fabrication process of the access transistors causes the cell to have a larger area.